1 ? fn4099.3 hs-1135rh radiation hardened, high speed, low power current feedba ck amplifier with programmable output limiting the hs-1135rh is a radiation hardened, high speed, low power current feedback amplif ier built with intersil?s proprietary complementary bipolar uhf-1 (di bonded wafer) process. they are qml approved and processed in full compliance with mil-prf-38535. this amplifier features user programmable output limiting, via the v h and v l pins. the hs-1135rh is the ideal choice for high speed, low power applications requiring ou tput limiting (e.g., flash a/d drivers), especially those requiring fast overdrive recovery times. the limiting function a llows the designer to set the maximum and minimum output levels to protect downstream stages from damage or input saturation. the sub-nanosecond overdrive recovery time ensures a quick return to linear operation following an overdrive condition. component and composite video systems also benefit from this op amp?s performance, as indicated by the gain flatness, and differential gain and phase specifications. specifications for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-96767. a ?hot-link? is provided on our website for downloading. features ? electrically screened to smd # 5962-96767 ? qml qualified per mil-prf-38535 requirements ? user programmable output voltage limiting ? fast overdrive recovery . . . . . . . . . . . . . . . . . <1ns (typ) ? low supply current . . . . . . . . . . . . . . . . . . . . 6.9ma (typ) ? wide -3db bandwidth. . . . . . . . . . . . . . . . . .360mhz (typ) ? high slew rate . . . . . . . . . . . . . . . . . . . . .1200v/s (typ) ? high input impedance . . . . . . . . . . . . . . . . . . . 2m (typ) ? excellent gain flatness (to 50mhz). . . . . . 0.07db (typ) ? total gamma dose . . . . . . . . . . . . . . . . . . . 300krad(si) ? latch up. . . . . . . . . . . . . . . . . . . . . none (di technology) applications ? flash a/d driver ? video switching and routing ? pulse and video amplifiers ? wideband amplifiers ? rf/if signal processing ? imaging systems pinouts hs-1135rh gdip1-t8 (cerdip) or cdip2-ti (sbdip) top view hs-1135rh cdfp3-f14 (flatpack) top view nc -in +in v- 1 2 3 4 8 7 6 5 v h v+ out v l + - 14 13 12 11 10 9 8 2 3 4 5 6 7 1 nc nc -in +in nc nc v- nc v h v+ out v l nc nc data sheet april 6, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1999, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn4099.3 april 6, 2009 ordering information ordering number (note) internal mkt. number part marking temp. range (c) package pkg dwg # 5962f9676701vpc hs7b-1135rh-q q5962f96 76701vpc -55 to +125 8 ld sbdip d8.3 5962f9676701vxc hs9-1135rh-q q5962f96 76701vxc -55 to +125 8 ld flatpack k14.a hs7b-1135rh/proto hs7b-1135rh/proto hs7b- 1135rh /proto -55 to +125 8 ld sbdip d8.3 hs9-1135rh/proto hs9-1135rh/proto hs9- 1135rh /proto -55 to +125 8 ld flatpack k14.a note: these intersil pb-free hermetic packaged products employ 100% au plate - e4 term ination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. hs-1135rh
3 fn4099.3 april 6, 2009 clamp operation general the hs-1135rh features user programmable output clamps to limit output voltage excursions. clamping action is obtained by applying voltages to the v h and v l terminals (pins 8 and 5) of the amplifier. v h sets the upper output limit, while v l sets the lower clamp level. if the amplifier tries to drive the output above v h , or below v l , the clamp circuitry limits the output voltage at v h or v l ( the clamp accuracy), respectively. the low input bias currents of the clamp pins allow them to be driven by simple resistive divide r circuits, or active elements such as amplifiers or dacs. clamp circuitry figure 1 shows a simplified sc hematic of the hs-1135rh input stage, and the high clamp (v h ) circuitry. as with all current feedback amplifiers, there is a unity gain buffer (q x1 - q x2 ) between the positive and negative inputs. this buffer forces -in to track +in, and sets up a slewing current of (v -in -v out )/r f . this current is mirrored onto the high impedance node (z) by q x3 -q x4 , where it is converted to a voltage and fed to the output via another unity gain buffer. if no clamping is utilized, the high impedance node may swing within the limits defined by q p4 and q n4 . note that when the output reaches it?s quiescent value, the current flowing through -in is reduced to only that small current (-i bias ) required to keep the output at the final voltage. tracing the path from v h to z illustrates the effect of the clamp voltage on the high impedance node. v h decreases by 2v be (qn6 and qp6) to set up the base voltage on qp5. qp5 begins to conduct whenever the high impedance node reaches a voltage equal to qp5?s base + 2v be (qp5 and qn5). thus, qp5 clamps node z whenever z reaches v h . r1 provides a pull-up network to ensure functionality with the clamp inputs floating. a similar description applies to the symmetrical low clamp circuitry controlled by v l . when the output is clamped, the negative input continues to source a slewing current (i clamp ) in an attempt to force the output to the quiescent voltage defined by the input. q p5 must sink this current while clampi ng, because the -in current is always mirrored onto the high impedance node. the clamping current is calculated as (v -in - v out )/r f . as an example, a unity gain circuit with v in = 2v, v h = 1v, and r f = 510 would have i clamp = (2-1)/510 = 1.96ma. note that i cc will increase by i clamp when the output is clamp limited. clamp accuracy the clamped output voltage will not be exactly equal to the voltage applied to v h or v l . offset errors, mostly due to v be mismatches, necessitate a clamp accuracy parameter which is found in the device specifications . clamp accuracy is a function of the clamping conditions. referring again to figure 1, it can be seen that one component of clamp accuracy is the v be mismatch between the q x6 transistors, and the q x5 transistors. if the transistors always ran at the same current level, there would be no v be mismatch, and no contribution to the inaccuracy. the q x6 transistors are biased at a constant current, but as described earlier, the current through q x5 is equivalent to i clamp . v be increases as i clamp increases, causing the clamped output voltage to increase as well. i clamp is a function of t he overdrive level (v -in -v outclamped ) and r f , so clamp accuracy degrades as the overdrive increases, or as r f decreases. as an example, the specified accuracy of 60mv for a 2x overdrive with r f =510 degrades to 220mv for r f =240 at the same overdrive, or to 250mv for a 3x overdrive with r f =510 . consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity. clamp range unlike some competitor devices, both v h and v l have usable ranges that cross 0v. while v h must be more positive than v l , both may be positive or negative, within the range restrictions indicated in the specifications. for example, the hs-1135rh could be limited to ecl output levels by setting v h = -0.8v and v l = -1.8v. v h and v l may be connected to the same voltage (gnd for instance) but the result won?t be in a dc output voltage from an ac input signal. a 150 - 200mv ac signal will still be present at the output. recovery from overdrive the output voltage remains at t he clamp level as long as the overdrive condition remains. when the input voltage drops below the overdrive level (v clamp /a vcl ) the amplifier will return to linear operation. a time delay, known as the overdrive recovery time, is re quired for this resumption of linear operation. the plots of ?unclamped performance? and ?clamped performance? high light the hs-1135rh?s sub nanosecond recovery time. the difference between the unclamped and clamped propagation delays is the overdrive +1 +in v- v+ q p1 q n1 v- q n3 q p3 q p4 q n2 q p2 q n4 q p5 q n5 z v+ -in v out i clamp r f (external) q p6 q n6 v h r 1 50k (30k for v l ) 200 figure 1. hs-1135rh simplified v h clamp circuitry hs-1135rh
4 fn4099.3 april 6, 2009 recovery time. the appropriate propagation delays are 4.0ns for the unclamped pulse, and 4.8ns for the clamped (2x overdrive) pulse yielding an overdrive recovery time of 800ps. the measurement uses t he 90% point of the output transition to ensure that linear operation has resumed. note: the propagation delay illustrated is dominated by the fixturing. the delta shown is accurate, but the true hs-1135rh propagation delay is 500ps. use of die in hy brid applications this amplifier is designed with compensation to negate the package parasitics that typicall y lead to instabilities. as a result, the use of die in hybrid applications results in overcompensated performance due to lower parasitic capacitances. reducing r f below the recommended values for packaged units will solve the problem. for a v = +2 the recommended starting point is 300 , while unity gain applications should try 400 . pc board layout the frequency performance of this amplifier depends a great deal on the amount of care taken in designing the pc board. the use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10f) tantalum in parallel with a small value chip (0.1f) capacitor wo rks well in most cases. terminated microstrip signal lines are recommended at the input and output of the device. output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and may cause oscillations. in most cases, the oscillation can be avoided by placing a resistor in series with the output. care must also be taken to minimize the capacitance to ground seen by the amplifier?s inverting input. the larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. to this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible. an example of a good high frequency layout is the evaluation board shown in figure 2. evaluation board an evaluation board is available for the hs-1135rh, (hfa11xxeval). please contact your local sales office for information. the layout and schematic of the board are shown in the following: figure 2a. top layout figure 2b. bottom layout figure 2c. schematic figure 2. evaluation board schematic and layout v h +in v l v+ gnd 1 v- out 1 2 3 4 8 7 6 5 +5v 10 f 0.1 f v h 50 gnd gnd 500 500 -5v 0.1 f 10 f 50 in out v l hs-1135rh
5 fn4099.3 april 6, 2009 burn-in circuit hs-1135rh cerdip notes: 1. r 1 = 1k , 5% (per socket) 2. r 2 = 10k , 5% (per socket) 3. c 1 = 0.01 f (per socket) or 0.1 f (per row) minimum 4. d 1 = 1n4002 or equivalent (per board) 5. d 2 = 1n4002 or equivalent (per socket) 6. v+ = +5.5v 0.5v 7. v- = -5.5v 0.5v irradiation circuit hs-1135rh cerdip notes: 8. r 1 = 1k , 5% 9. r 2 = 10k , 5% 10. c 1 = c 2 = 0.01 f 11. v+ = +5.0v 0.5v 12. v- = -5.0v 0.5v 1 2 3 4 8 7 6 5 v+ c 1 d 1 d 1 c 1 v- d 2 d 2 r 2 r 1 r 1 + - 1 2 3 4 8 7 6 5 v+ c 1 c 2 v- r 2 r 1 r 1 - + hs-1135rh
6 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn4099.3 april 6, 2009 die characteristics die dimensions: 59 mils x 58.2 mils x 19 mils 1 mil 1500m x 1480m x 483m 25.4m interface materials: glassivation: type: nitride thickness: 4k ? 0.5k ? top metallization: type: metal 1: aicu(2%)/tiw thickness: metal 1: 8k ? 0.4k ? type: metal 2: aicu(2%) thickness: metal 2: 16k ? 0.8k ? substrate: uhf-1, bonded wafer, di assembly related information: substrate potential: floating additional information: worst case current density: < 2 x 10 5 a/cm 2 transistor count: 89 metallization mask layout hs-1135rh v- out +in -in v+ v l v h hs-1135rh
7 fn4099.3 april 6, 2009 hs-1135rh ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f8.3a mil-std-1835 gdip1-t8 (d-4, configuration a) 8 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d- 0.405 - 10.29 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 -7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m- 0.0015 - 0.038 2, 3 n8 88 rev. 0 4/94
8 fn4099.3 april 6, 2009 hs-1135rh ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d8.3 mil-std-1835 cdip2-t8 (d-4, configuration c) 8 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d- 0.405 - 10.29 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 -6 s2 0.005 - 0.13 -7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m- 0.0015 - 0.038 2 n8 88 rev. 0 4/94
9 fn4099.3 april 6, 2009 hs-1135rh ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f-2a, configuration b) 14 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d- 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 - 0.290 - 7.11 3 e2 0.125 - 3.18 -- e3 0.030 - 0.76 -7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 -6 m- 0.0015 - 0.04 - n14 14- rev. 0 5/18/94
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